Via, trench or contact structure in the metallization, prematallization dielectric or interlevel dielectric layers of an integrated circuit

ABSTRACT

A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application for patent Ser.No. 14/724,975 filed May 29, 2015, the disclosure of which is herebyincorporated by reference.

TECHNICAL FIELD

The present invention relates to integrated circuits and, in particular,to the formation of metal-filled vias, trenches or contact openings inthe metallization (M), premetallization dielectric (PMD) or interleveldielectric (ILD) layers of an integrated circuit.

BACKGROUND

Reference is now made to FIG. 1 showing the general configuration of aconventional metal oxide semiconductor (MOS) field effect transistor(FET) 10 device. A substrate 12 supports the transistor. In thisexample, the substrate is of the silicon-on-insulator substrate 12 typewhich includes a substrate layer 14, a buried oxide (BOX) layer 16 and asemiconductor layer 18. An active region 20 for the transistor device isdelimited by a peripherally surrounding shallow trench isolation 22 thatpenetrates through the layer 18. Within the active region 20, the layer18 is divided into a channel region 30 which has been doped with a firstconductivity type dopant, a source region 32 (adjacent the channelregion 30 on one side) which has been doped with a second conductivitytype dopant, and a drain region 34 (adjacent the channel region 30 on anopposite side from the source region 32) which has also been doped withthe second conductivity type dopant. Where the MOSFET 10 device is ofthe p-channel type, the first conductivity type dopant is p-type and thesecond conductivity type is n-type. Conversely, where the MOSFET deviceis of the n-channel type, the first conductivity type dopant is n-typeand the second conductivity type is p-type. A gate stack 36 is providedabove the channel region 30. This gate stack 36 typically comprises agate dielectric 38, a gate electrode 40 (for example, of metal and/orpolysilicon material) and sidewall spacers 42 made of an insulatingmaterial such as silicon nitride (SiN) deposited on the sides of thegate dielectric 38 and gate electrode 40. An interlevel dielectric (ILD)or pre-metallization dielectric (PMD) layer 46 is provided above thesubstrate and the gate stack. A top surface 48 of the layer 46 isprocessed with a chemical-mechanical polishing (CMP) process to define aplanar surface. A set of metal contacts 50, typically formed oftungsten, extend from the top surface 48 through the ILD/PMD layer 46 inmetal-filled contact openings to make electrical contact with the sourceregion 32, drain region 34 and gate electrode 40. A first metallizationlayer M1 is then provided above the ILD/PMD layer 46, with the firstmetallization layer M1 comprising metal lines 54 formed in metal-filledvia and/or trench openings in contact with the contacts 50 andsurrounded by a planarized dielectric material layer 56.

As feature sizes in integrated circuit devices continue to shrink andoperational speed increases, there is a need to make a thicker ILD/PMDlayer 46 so as to reduce capacitance between the first metallizationlayer M1 and the active region 20 as well as between the firstmetallization layer M1 and the gate electrode 40. The thicker ILD/PMDlayer 46 and reduced feature size accordingly necessitates the use ofhigh aspect ratio metal contacts 50 (i.e., contacts made in openingswith a height/width ratio >>1, for example, ≥4). It is a challenge toprovide such high aspect ratio contacts without incurring problemsassociated with open yield and increased contact resistance. There isaccordingly a need in the art for an improved contact configuration forinterconnecting the first metallization layer M1 to both the activeregion 20 and the gate electrode 40.

In addition, improved structures for the metal lines and metal vias inthe metallization layers of integrated circuits are needed to ensuredevice reliability and improve signal performance through resistanceadjustment.

SUMMARY

In an embodiment, an integrated circuit comprises: a substrate; andconductive interconnect structures over the substrate, said conductiveinterconnect structures including a first interconnect structure and asecond interconnect structure; wherein: the first interconnect structureis adjacent to the second interconnect structure; the first interconnectstructure includes a first substructure at a first level and a secondsubstructure at a second level, the second level located at a greaterdistance from the substrate than the first level; the secondsubstructure of the first interconnect structure is electrically coupledto the first substructure of the first interconnect structure; thesecond interconnect structure includes a first substructure at the firstlevel and a second substructure at the second level; the secondsubstructure of the second interconnect structure is electricallycoupled to the first substructure of the second interconnect structure;the first substructure of the first interconnect structure has a lengthgreater than a length of the first substructure of the secondinterconnect structure; and the second substructure of the secondinterconnect structure having a length greater than a length of thesecond substructure of the first interconnect structure.

In an embodiment, an integrated circuit comprises: a substrate; andconductive interconnect structures over the substrate, said conductiveinterconnect structures including a first interconnect structure and asecond interconnect structure; and wherein: the first interconnectstructure is adjacent the second interconnect structure; the firstinterconnect structure includes a first substructure at a first leveland a second substructure at a second level, the second level located ata greater distance from the substrate than the first level; the secondsubstructure of the first interconnect structure is electrically coupledto the first substructure of the first interconnect structure; thesecond interconnect structure includes a first substructure at the firstlevel and a second substructure at the second level; the secondsubstructure of the second interconnect structure is electricallycoupled to the first substructure of the second interconnect structure;and wherein a first distance between the first substructure of the firstinterconnect structure and the second substructure of the secondinterconnect structure is less than a second distance between the firstsubstructure of the first interconnect structure and the firstsubstructure of the second interconnect structure.

In an embodiment, an integrated circuit comprises: a substrate; andconductive interconnect structures over the substrate, said conductiveinterconnect structures including a first interconnect structure and asecond interconnect structure; and wherein: the first interconnectstructure is adjacent to the second interconnect structure; the firstinterconnect structure includes a first substructure at a first leveland a second substructure at a second level, the second level located ata greater distance from the substrate than the first level; the secondsubstructure of the first interconnect structure is electrically coupledto the first substructure of the first interconnect structure; thesecond interconnect structure includes a first substructure at the firstlevel and a second substructure at the second level; the secondsubstructure of the second interconnect structure is electricallycoupled to the first substructure of the second interconnect structure;the first substructure of the first interconnect structure has a lengthgreater than a length of the first substructure of the secondinterconnect structure; the second substructure of the secondinterconnect structure having a length greater than a length of thesecond substructure of the first interconnect structure; and wherein afirst distance between the first substructure of the first interconnectstructure and the second substructure of the second interconnectstructure is less than a second distance between the first substructureof the first interconnect structure and the first substructure of thesecond interconnect structure.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the embodiments, reference will now bemade by way of example only to the accompanying figures in which:

FIG. 1 illustrates the configuration of a prior art MOSFET device; and

FIGS. 2A-2D illustrate the configuration of contacts in accordance withan embodiment implemented with an example of a MOSFET device;

FIG. 3 illustrates a perspective view of the gate electrode and thecontacts for the configuration shown in FIGS. 2A-2D;

FIGS. 4A-4D illustrate the configuration of contacts in accordance withan embodiment implemented with an example of a MOSFET device;

FIG. 5 illustrates a perspective view of the gate electrode and thecontacts for the configuration shown in FIGS. 4A-4D;

FIGS. 6-8 illustrates perspective views of alternative arrangements ofthe contacts; and

FIG. 9 illustrates the configuration of metal-filled vias and trenchesfor a metallization layer of an integrated circuit;

FIG. 10 illustrates a perspective view of certain structures shown inFIG. 9;

FIG. 11 illustrates a perspective view of an alternate structure.

The illustrations provided are not necessarily drawn to scale.

DETAILED DESCRIPTION OF THE DRAWINGS

Reference is now made to FIGS. 2A-2D which illustrate the configurationof contacts in accordance with an embodiment implemented with an exampleof a MOSFET device 110 as an integrated circuit. FIGS. 2A-2B areparallel cross-sectional views taken offset from each other in adirection into/out of the page. FIGS. 2C-2D are parallel cross-sectionalviews taken offset from each other in a direction into/out of the page,with the views of FIGS. 2C-2D being orthogonal to the views of FIGS.2A-2B.

A substrate 112 supports the MOSFET device 110. In this example, thesubstrate is of the silicon-on-insulator substrate 112 type whichincludes a substrate layer 114, a buried oxide (BOX) layer 116 and asemiconductor layer 118 (although it will be understood that thefeatures disclosed herein are equally applicable to integrated circuitsfabrication with a bulk or other semiconductor substrate as support). Anactive region 120 for the transistor device is delimited by aperipherally surrounding shallow trench isolation 122 that penetratesthrough the layer 118. Within the active region 120, the layer 118 isdivided into a channel region 130 which has been doped with a firstconductivity type dopant, a source region 132 (adjacent the channelregion 130 on one side) which has been doped with a second conductivitytype dopant, and a drain region 134 (adjacent the channel region 130 onan opposite side from the source region 132) which has also been dopedwith the second conductivity type dopant. Where the MOSFET 110 device isof the p-channel type, the first conductivity type dopant is p-type andthe second conductivity type is n-type. Conversely, where the MOSFETdevice is of the n-channel type, the first conductivity type dopant isn-type and the second conductivity type is p-type. A gate stack 136 isprovided above the channel region 130. This gate stack 136 typicallycomprises a gate dielectric 138, a polysilicon material gate electrode140 and sidewall spacers 142 made of an insulating material such assilicon nitride (SiN) deposited on the sides of the gate dielectric 138and polysilicon material gate electrode 140. An interlevel dielectric(ILD) or pre-metallization dielectric (PMD) layer 146 is provided abovethe substrate and the gate stack. A top surface 148 of the layer 146 isprocessed with a chemical-mechanical polishing (CMP) process to define aplanar surface.

The ILD/PMD layer 146 comprises a plurality of sub-layers including: afirst sub-layer 146(1), a second sub-layer 146(2) and a third sub-layer146(3). Although three sub-layers are shown, it will be understood thatlayer 146 may comprise more sub-layers than three if demanded by theapplication and the geometry of the device. The first sub-layer 146(1)has a thickness which is generally the same as a thickness of the gatestack 136. This is not a requirement, but in many instances thesub-layer 146(1) is deposited and chemically-mechanically polished (CMP)stopping at the top of the gate stack 136. This operation may beperformed in connection with implementation of replacement gateprocesses as known in the art. The second and third sub-layers 146(2)and 146(3) may have thicknesses as desired, which may be thicker,thinner or generally equal to the thickness of the first sub-layer146(1). These additional sub-layers beyond sub-layer 146(1) are providedto increase the thickness of the layer 146 to a desired thicknessseparating the substrate from back-end-of-line (BEOL) structures such asmetallization layers.

A set of metal contacts 150, typically formed of tungsten, extend fromthe top surface 148 through the ILD/PMD layer 146 to make electricalcontact with each of the source region 132 and drain region 134. A metalcontact 152, typically formed of tungsten, extends from the top surface148 through the ILD/PMD layer 146 to make electrical contact with thegate electrode 140.

With respect to the contacts (also referred to as interconnectstructures) 150 for the source region 132 and drain region 134, a firstsub-contact (or substructure) 150(1) is provided in the first sub-layer146(1). The first sub-contact 150(1) has a thickness equal to thethickness of the first sub-layer 146(1). The first sub-contact 150(1)has a first width as shown in FIG. 2A and a first length as shown inFIG. 2C.

Additionally, a second sub-contact 150(2) is provided in the secondsub-layer 146(2). The second sub-contact 150(2) has a thickness equal tothe thickness of the second sub-layer 146(2). The second sub-contact150(2) has a second width as shown in FIG. 2A and a second length asshown in FIG. 2C which is different from the first length. The secondwidth may, for example, equal the first width and the second length maybe less than the first length.

Additionally, a third sub-contact 150(3) is provided in the thirdsub-layer 146(3). The third sub-contact 150(3) has a thickness equal tothe thickness of the third sub-layer 146(3). The third sub-contact150(3) has a third width as shown in FIG. 2A and a third length as shownin FIG. 2C different from the first and second lengths. The third widthmay, for example, equal the first and second widths and the third lengthmay be less than the second length.

The first, second and third sub-contacts 150(1)-150(3) are in serieselectrical connection with each other to define the contact 150 whichextends from the top surface 148 through the ILD/PMD layer 146 to makephysical and electrical contact with the source region 132 or drainregion 134. It will be noted that the lengths of the sub-contacts 150progressively decrease in size the further the sub-contact is from theplanar surface 148.

With respect to the contact (also referred to as an interconnectstructure) 152 for the gate electrode 140, a first sub-contact (orsubstructure) 152(1) is provided in the second sub-layer 146(2). Thefirst sub-contact 152(1) has a thickness equal to the thickness of thesecond sub-layer 146(2). The first sub-contact 152(1) has a first widthas shown in FIG. 2D and a first length as shown in FIG. 2B.

Additionally, a second sub-contact 152(2) is provided in the thirdsub-layer 146(3). The second sub-contact 152(2) has a thickness equal tothe thickness of the third sub-layer 146(3). The second sub-contact152(2) has a second width as shown in FIG. 2D and a second length asshown in FIG. 2B different from the first length. The second width may,for example, equal the first width and the second length may be greaterthan the first length.

The first and second sub-contacts 152(1)-152(2) are in series electricalconnection with each other to define the contact 150 which extends fromthe top surface 148 through the ILD/PMD layer 146 to make physical andelectrical contact with the gate electrode 140. It will be noted thatthe lengths of the sub-contacts 152 progressively increase in size thefurther the sub-contact is from the planar surface 148.

In an embodiment, a volume of conductive material for the contact 150(to either the source region or drain region) is substantially equal toa volume of conductive material for the contact 152 (to the gateregion). In this context, the volumes of conductive material areconsidered to be substantially equal if they are within 5% of eachother. To accomplish this design goal, the layout designer selects thewidths and lengths of the sub-contacts for each of the sub-layers.

A first metallization layer M1 is then provided at the top surface 148of the ILD/PMD layer 146, with the first metallization layer M1comprising metal lines 154 in contact with the contacts 150 and 152 andsurrounded by a planarized dielectric material layer 156. Additionalmetallization layers (not shown) may be provided above the firstmetallization layer M1 in a manner well known in the art. Themetallization layers may, for example, be formed using well knowndamascene processes. The metal lines 154 of the metallization layer M1are configured to make physical and electrical contact to a plurality ofcontacts such as, for example, shown in FIG. 2C at reference 180 withmetal line 154 making electrical connection through contacts to twodifferent source regions 132. The illustration of source region contactis by example only as the metal lines of the metallization layer M1 maybe provided to make contact to multiple drain regions, multiple gateregions or multiple combinations of source, drain and gate regions inaccordance with the integrated circuit design.

FIG. 3 illustrates a perspective view of the gate electrode 140 and thecontacts 150 and 152 for the configuration shown in FIGS. 2A-2D. Thecontacts 150 are shown in contact with and extending upwardly from thesource region 132 and drain region 134 formed in the substrate 112semiconductor layer 118. The contact 152 is shown in contact with andextending upwardly from the gate electrode 140 formed above thesubstrate 112 semiconductor layer 118.

In an embodiment utilizing a replacement metal gate technology, the gateelectrode 140 may instead comprise a metal fill material 140′ as shownin FIGS. 4A-4D with FIG. 5 illustrating a perspective view of the gateelectrode 140′ and the contacts 150 and 152. Like reference numbersrefer to like or similar parts as described above.

In this configuration, with respect to the contacts 152 for the gateelectrode, a first sub-contact 152(1) comprising the replacement metalgate 140′ is provided in the first sub-layer 146(1). The firstsub-contact 150(1) has a thickness generally equal to the thickness ofthe first sub-layer 146(1) (taking into account other structures of thegate stack such as the gate dielectric and work function metal, forexample). The first sub-contact 150(1) has a first width as shown inFIG. 4D and a first length as shown in FIG. 4B.

Additionally, a second sub-contact 152(2) is provided in the secondsub-layer 146(2). The second sub-contact 152(2) has a thickness equal tothe thickness of the second sub-layer 146(2). The second sub-contact152(2) has a second width as shown in FIG. 4D and a second length asshown in FIG. 4B. It will be note in this implementation the length ofthe second sub-contact 152(2) extends perpendicular to the length of thefirst sub-contact 152(1). The length of the second sub-contact 152(2) islikely to be different from the length of the first sub-contact 152(1).The second width may, for example, equal the first width and the secondlength may be greater than or less than the first length depending onapplication.

Additionally, a third sub-contact 152(3) is provided in the thirdsub-layer 146(3). The third sub-contact 152(3) has a thickness equal tothe thickness of the third sub-layer 146(3). The third sub-contact152(3) has a third width as shown in FIG. 4D and a third length as shownin FIG. 4B which is different from the second length. The third widthmay, for example, equal the first and second widths and the third lengthmay be greater than the second length.

Although the contacts 150 and 152 are shown in FIGS. 3 and 5 to extendin their lengths generally perpendicular to each other, it will beunderstood that this is not a requirement. FIG. 6 illustrates aperspective view of the contacts 150 and 152 in a configuration wherethe lengths of the contacts extend parallel to each other. FIG. 6further shows contact 150 in contact with and extending upwardly from afirst region 132′ formed in the substrate 112 semiconductor layer 118,and shows contact 152 in contact with and extending upwardly from asecond region 134′ formed in the substrate 112 semiconductor layer 118.The regions 132′ and 134′ may, for example, comprise source and drainregions, respectively, of a transistor device. The regions 132′ and 134′may alternatively comprise any substrate region in an integrated circuitdevice (for example, bipolar transmitter emitter region, bipolartransmitter base region, bipolar transmitter collector region, FinFETstructure regions, or UTBB/ETSOI planar source, drain or gate regions).It will further be noted that the lengths of the sub-contacts aredifferent with respect to each of the sub-contacts forming a contact.For one contact (for example, contact 150), the lengths increase movingaway from the substrate doped region 132′, and for another contact (forexample, contact 152), the lengths decrease moving away from thesubstrate doped region 134′. In an embodiment, as shown in FIG. 6, thesub-contacts on different sub-layers may be configured to overlap eachother as indicated at reference 168 in a direction perpendicular to thesurface of the substrate.

While rectangular prism structures are shown in FIGS. 3 and 5-6, it willbe understood this is just an example of the shape which may be used forthe contacts 150 and 152. FIG. 7 illustrates a perspective view of thecontacts 150 and 152 utilizing a circular prism (cylindrical) shape. Inthis implementation, it will be noted that the lengths (specifically,the diameters) of the sub-contacts are different with respect to each ofthe sub-contacts forming a contact. For one contact (for example,contact 150), the lengths (diameters) decrease moving away from thesubstrate doped region 132′, and for another contact (for example,contact 152), the lengths (diameters) increase moving away from thesubstrate doped region 134′.

FIG. 8 shows contacts 150 and 152 in a perpendicular orientation likethat shown in FIGS. 3 and 5. It will further be noted that the lengthsof the sub-contacts are different with respect to each of thesub-contacts forming a contact. For one contact (for example, contact150), the lengths increase moving away from the substrate doped region132′, and for another contact (for example, contact 152), the lengthsdecrease moving away from the substrate doped region 134′. FIG. 8further shows, at reference 168, a perpendicular overlap with respect tosub-contacts in different sub-layers.

It will be noted that a volume of conductive material in the first andsecond contacts of the implementations shown in FIGS. 6-8 is preferablysubstantially equal. In this context, the volumes of conductive materialare considered to be substantially equal if they are within 5% of eachother.

In an embodiment, the first sub-contact 150(1) and the first sub-contact152(1) in any of the disclosed implementations may be made of a firstmetal material such as, for example, tungsten. The remainingsub-contacts, such as the second and third sub-contacts 150(2)-150(3)and second and third sub-contacts 152(2) and 152(3) may be made of thesame first material or, in an alternative implementation, made of asecond metal material such as, for example, copper. In this regard, themetal material used for the metal lines 154 of the metallization layerM1 may also comprise, for example, copper. This use of the first metalmaterial (tungsten) is consistent with the use of tungsten material forcontacts and replacement metal gate structures at the first sub-layer,while the use of the second material (copper) for the sub-contacts inthe remaining sub-layers supports the known advantages of copper use forwiring lines in integrated circuit devices. Aluminum presents analternative second material choice.

Each of the sub-contacts may further include a barrier liner (forexample, made of titanium nitride (TiN)) to protect against diffusion ofthe metal species used for the sub-contact into the sub-layers of theILD/PMD layer 146.

Conventional deposit, pattern and fill process steps may be used toproduce the sub-layers and sub-contacts. For example, a mask definingthe location of openings for the sub-contacts may be produced on top ofa given sub-layer of the ILD/PMD layer 146. An opening is then formed inthat given sub-layer using the mask and a reactive ion etch (ME) isperformed through the mask. The etch should extend completely throughthe given sub-layer to form the opening. An atomic layer deposition(ALD) technique is then used to deposit the metal barrier liner (such asTiN) on the walls of the opening, and a metal filling process (such asthermal chemical vapor deposition (CVD)) is then used to fill theopening with the metal material of the sub-contact (such as tungsten orcopper). A chemical-mechanical polishing (CMP) process is then performedto remove excess metal barrier and fill material, with the CMP stoppingat the top of the given sub-layer of the ILD/PMD layer 146. A chemicalvapor deposition (CVD) process is then performed to deposit the nextsub-layer of the ILD/PMD layer 146. The previous steps are then repeatedto form the sub-contact in that next sub-layer. The process may berepeated as many times as are necessary to define the thickness of theILD/PMD layer 146 from multiple deposited, patterned and filledsub-layers with sub-contacts. For example, the ILD/PMD layer 146 mayhave a thickness of 120-140 nm, with each sub-layer having a thicknessof between 30-100 nm. The minimum width of the sub-contacts is set bythe minimum dimension of the lithographic process used for fabrication.Conventional back-end-of-line (BEOL) processes are then performed toprovide the necessary metallization levels.

Although specific reference is made herein to a planar MOSFET device andthe formation of contacts for source, drain and gate, it will beunderstood that the techniques and structures for contacts describedherein are applicable to an integrated circuit device including, withoutlimitation, bipolar transistor devices, FinFET devices, diode devices,planar transistor devices with source and drain regions formed from UTBBor ETSOI substrates, and the like.

The structures described above for use as contacts in the ILD/PMD layer146 may be advantageously extended for use in metallization layers.Reference is accordingly made to FIG. 9 which illustrates theconfiguration of metal-filled vias and trenches for a metallizationlayer M1 of an integrated circuit. The metallization layer M1 includes adielectric material layer 156 having a planar top surface 158 that isformed on the top surface 148 of the ILD/PMD layer 146. Metal lines154(1) and 154(2), typically formed of copper or aluminum, are formed inthe dielectric material layer 156 to extend from the top surface 158 tothe top surface 148 in order to make physical and electrical connectionto contacts 150 and/or 152.

FIG. 9 shows the structures in the substrate and the ILD/PMD layer 146as presented in FIGS. 2A-2D, but it will be understood that thestructures as shown in FIGS. 4A-4D are equally applicable.

The dielectric material layer 156 comprises a plurality of sub-layersincluding: a first sub-layer 156(1), a second sub-layer 156(2) and athird sub-layer 156(3). Although three sub-layers are shown, it will beunderstood that layer 156 may comprise more sub-layers than three ifdemanded by the application and the geometry of the device. The first,second and third sub-layers 156(1), 156(2) and 156(3) may have differentor substantially same thicknesses as desired by the application androuting of wiring.

Although disclosed in the context of the M1 metallization layer, it willbe understood that the sub-layers are equally applicable to any of theincluded further metallization layers (M2-Mn) required by the integratedcircuit.

With respect to the metal line (also referred to as an interconnectstructure) 154(1), a first sub-line (or substructure) 164(1) is providedin the first sub-layer 156(1). The first sub-line 164(1) has a thicknessequal to the thickness of the first sub-layer 156(1). The first sub-line164(1) has a first width and a first length.

Additionally, a second sub-line 164(2) is provided in the secondsub-layer 156(2). The second sub-line 164(2) has a thickness equal tothe thickness of the second sub-layer 156(2). The second sub-line 164(2)has a second width which is different from the first width and a secondlength. The second width may, for example, be less than the first widthand the second length may be equal to the first length.

Additionally, a third sub-line 164(3) is provided in the third sub-layer156(3). The third sub-line 164(3) has a thickness equal to the thicknessof the third sub-layer 156(3). The third sub-line 164(3) has a thirdwidth different from the first and second widths and a third length. Thethird width may, for example, be less than the first and second widthsand the third length may be equal to the second length.

The first, second and third sub-lines 164(1)-164(3) are in serieselectrical connection with each other to define the first line 154(1)which extends from the top surface 158 through the dielectric layer 156to make physical and electrical contact with the contact 150 for thesource region 132. It will be noted that the widths of the sub-lines 164progressively decrease in size the further the sub-line is from theplanar surface 148.

With respect to the metal line 154(2), a first sub-line 164(1) isprovided in the first sub-layer 156(1). The first sub-line 164(1) has athickness equal to the thickness of the first sub-layer 156(1). Thefirst sub-line 164(1) has a first width and a first length.

Additionally, a second sub-line 164(2) is provided in the secondsub-layer 156(2). The second sub-line 164(2) has a thickness equal tothe thickness of the second sub-layer 156(2). The second sub-line 164(2)has a second width which is different from the first width and a secondlength. The second width may, for example, greater than the first widthand the second length may be equal to the first length.

Additionally, a third sub-line 164(3) is provided in the third sub-layer156(3). The third sub-line 164(3) has a thickness equal to the thicknessof the third sub-layer 156(3). The third sub-line 164(3) has a thirdwidth different from the first and second widths and a third length. Thethird width may, for example, be greater than the first and secondwidths and the third length may be equal to the second length.

The first, second and third sub-lines 164(1)-164(3) are in serieselectrical connection with each other to define the second line 154(2)which extends from the top surface 158 through the dielectric layer 156to make physical and electrical contact with the contact 150 for thedrain region 134. It will be noted that the widths of the sub-lines 164progressively increase in size the further the sub-contact is from theplanar surface 148.

In an embodiment, a volume of conductive material for the first line154(1) is substantially equal to a volume of conductive material for thesecond line 154(2). In this context, the volumes of conductive materialare considered to be substantially equal if they are within 5% of eachother. To accomplish this design goal, the layout designer selects thewidths and lengths of the sub-lines for each of the sub-layers.

Additionally, the first and second sub-lines are positioned immediatelyadjacent each other without any intervening metal structure within saidsame dielectric layer 156. In this configuration, a first spacingdistance in a direction parallel to the planar surfaces between firstand second sub-lines on different sub-layers is less than a secondspacing distance the direction parallel to the planar surfaces betweenfirst and second sub-lines located on different sub-layers. Indeed, thisfirst spacing distance may be negative in that some overlap betweensub-lines on different sub-layers in the vertical directionperpendicular to the planar surfaces is provided. This overlap isgenerally indicated at reference 168.

FIG. 10 illustrates a perspective view of the contacts 150 and the lines154(1) and 154(2) for the configuration shown in FIG. 9 (wherein thestructures relating to the gate electrode and contact 152 are omitted tosimplify the illustration and ensure visibility of the structures forthe contacts 150 and the lines 154(1) and 154(2)).

Although the lines 154(1) and 154(2) are shown in FIG. 10 to extend intheir lengths generally parallel to each other, it will be understoodthat this is not a requirement. Instead, the lines 154(1) and 154(2)could extend in their lengths perpendicular to each other as shown inFIG. 11.

Each of the sub-lines may further include a barrier liner (for example,made of titanium nitride (TiN)) to protect against diffusion of themetal species used for the sub-line into the sub-layers of thedielectric material layer 156.

Conventional deposit, pattern and fill process steps may be used toproduce the sub-layers and sub-lines. For example, a mask defining thelocation of openings for the sub-lines may be produced on top of a givensub-layer of the dielectric material layer 156. An opening is thenformed in that given sub-layer using the mask and a reactive ion etch(ME) is performed through the mask. The etch should extend completelythrough the given sub-layer to form the opening. An atomic layerdeposition (ALD) technique is then used to deposit the metal barrierliner (such as TiN) on the walls of the opening, and a metal fillingprocess (such as thermal chemical vapor deposition (CVD)) is then usedto fill the opening with the metal material of the sub-line (such ascopper or aluminum). A chemical-mechanical polishing (CMP) process isthen performed to remove excess metal barrier and fill material, withthe CMP stopping at the top of the given sub-layer of the dielectricmaterial layer 156. A chemical vapor deposition (CVD) process is thenperformed to deposit the next sub-layer of the dielectric material layer156. The previous steps are then repeated to form the sub-line in thatnext sub-layer. The process may be repeated as many times as arenecessary to define the thickness of the metallization layer frommultiple deposited, patterned and filled sub-layers with sub-lines. Forexample, the metallization layer may have a thickness of 48 to 120 nm,with each sub-layer having a thickness of between 16 and 40 nm. Theminimum dimension of the sub-lines is set by the minimum dimension ofthe lithographic process used for fabrication.

The foregoing description has provided by way of exemplary andnon-limiting examples a full and informative description of theexemplary embodiment of this invention. However, various modificationsand adaptations may become apparent to those skilled in the relevantarts in view of the foregoing description, when read in conjunction withthe accompanying drawings and the appended claims. However, all such andsimilar modifications of the teachings of this invention will still fallwithin the scope of this invention as defined in the appended claims.

What is claimed is:
 1. An integrated circuit, comprising: a substrate;and conductive interconnect structures over the substrate, saidconductive interconnect structures including a first interconnectstructure and a second interconnect structure; and wherein: the firstinterconnect structure is adjacent to the second interconnect structure;the first interconnect structure includes a first substructure at afirst level and a second substructure at a second level, the secondlevel located at a greater distance from the substrate than the firstlevel; the second substructure of the first interconnect structure iselectrically coupled to the first substructure of the first interconnectstructure; the second interconnect structure includes a firstsubstructure at the first level and a second substructure at the secondlevel; the second substructure of the second interconnect structure iselectrically coupled to the first substructure of the secondinterconnect structure; the first substructure of the first interconnectstructure has a length greater than a length of the first substructureof the second interconnect structure; and the second substructure of thesecond interconnect structure having a length greater than a length ofthe second substructure of the first interconnect structure.
 2. Thecircuit of claim 1, wherein the second substructure of the firstinterconnect structure is electrically connected with the firstsubstructure of the first interconnect structure.
 3. The circuit ofclaim 1, wherein the second substructure of the first interconnectstructure is in physical contact with the first substructure of thefirst interconnect structure.
 4. The circuit of claim 1, wherein thesecond substructure of the second interconnect structure is electricallyconnected to the first substructure of the second interconnectstructure.
 5. The circuit of claim 1, wherein the second substructure ofthe second interconnect structure is in physical contact with the firstsubstructure of the second interconnect structure.
 6. The circuit ofclaim 1, wherein the second substructure of the first structure is inphysical contact with the first substructure of the first interconnectstructure, and wherein the second substructure of the secondinterconnect structure is in physical contact with the firstsubstructure of the second interconnect structure.
 7. The circuit ofclaim 1, wherein a first distance between the first substructure of thefirst interconnect structure and the second substructure of the secondinterconnect structure is less than a second distance between the firstsubstructure of the first interconnect structure and the firstsubstructure of the second interconnect structure.
 8. The circuit ofclaim 7, wherein a third distance between the first substructure of thesecond interconnect structure and the second substructure of the firstinterconnect structure is greater than the second distance.
 9. Thecircuit of claim 7, wherein a third distance between the firstsubstructure of the second interconnect structure and the secondsubstructure of the first interconnect structure is greater than thefirst distance.
 10. The circuit of claim 9, wherein the third distanceis greater than the second distance.
 11. The circuit of claim 1, whereinthe first and second interconnect structures are electrically insulatedfrom each other at both the first level and the second level.
 12. Thecircuit of claim 1, wherein the substrate includes a source region of atransistor and a drain region of said transistor, and wherein the firstinterconnect structure is electrically connected to the source regionand wherein the second interconnect structure is electrically connectedto the drain region.
 13. An integrated circuit, comprising: a substrate;and conductive interconnect structures over the substrate, saidconductive interconnect structures including a first interconnectstructure and a second interconnect structure; and wherein: the firstinterconnect structure is adjacent the second interconnect structure;the first interconnect structure includes a first substructure at afirst level and a second substructure at a second level, the secondlevel located at a greater distance from the substrate than the firstlevel; the second substructure of the first interconnect structure iselectrically coupled to the first substructure of the first interconnectstructure; the second interconnect structure includes a firstsubstructure at the first level and a second substructure at the secondlevel; the second substructure of the second interconnect structure iselectrically coupled to the first substructure of the secondinterconnect structure; and wherein a first distance between the firstsubstructure of the first interconnect structure and the secondsubstructure of the second interconnect structure is less than a seconddistance between the first substructure of the first interconnectstructure and the first substructure of the second interconnectstructure.
 14. The circuit of claim 13, wherein a third distance betweenthe first substructure of the second interconnect structure and thesecond substructure of the first interconnect structure is greater thanthe second distance.
 15. The circuit of claim 13, wherein a thirddistance between the first substructure of the second interconnectstructure and the second substructure of the first interconnectstructure is greater than the first distance.
 16. The circuit of claim15, wherein the third distance is greater than the second distance. 17.The circuit of claim 13, wherein the first substructure of the firstinterconnect structure has a length greater than a length of the firstsubstructure of the second interconnect structure, and the secondsubstructure of the second interconnect structure has a length greaterthan a length of the second substructure of the first interconnectstructure.
 18. An integrated circuit, comprising: a substrate; andconductive interconnect structures over the substrate, said conductiveinterconnect structures including a first interconnect structure and asecond interconnect structure; and wherein: the first interconnectstructure is adjacent to the second interconnect structure; the firstinterconnect structure includes a first substructure at a first leveland a second substructure at a second level, the second level located ata greater distance from the substrate than the first level; the secondsubstructure of the first interconnect structure is electrically coupledto the first substructure of the first interconnect structure; thesecond interconnect structure includes a first substructure at the firstlevel and a second substructure at the second level; the secondsubstructure of the second interconnect structure is electricallycoupled to the first substructure of the second interconnect structure;the first substructure of the first interconnect structure has a lengthgreater than a length of the first substructure of the secondinterconnect structure; the second substructure of the secondinterconnect structure having a length greater than a length of thesecond substructure of the first interconnect structure; and wherein afirst distance between the first substructure of the first interconnectstructure and the second substructure of the second interconnectstructure is less than a second distance between the first substructureof the first interconnect structure and the first substructure of thesecond interconnect structure.
 19. The circuit of claim 18, wherein athird distance between the first substructure of the second interconnectstructure and the second substructure of the first interconnectstructure is greater than the second distance.
 20. The circuit of claim19, wherein a third distance between the first substructure of thesecond interconnect structure and the second substructure of the firstinterconnect structure is greater than the first distance.
 21. Thecircuit of claim 20, wherein the third distance is greater than thesecond distance.
 22. The circuit of claim 18, wherein the secondsubstructure of the first structure is in physical contact with thefirst substructure of the first interconnect structure, and wherein thesecond substructure of the second interconnect structure is in physicalcontact with the first substructure of the second interconnectstructure.